A simulation is only as good as the models used in it. At Develeast we know the importance of having accurate yet flexible models that can be reused for different projects. That is why we have developed a series of models to check the functionalty and timings of some commonly used communication protocols and processor interfaces.

These models have been developed with the performance of the simulation in mind, they can be used in RTL as well as in Gate Level simulations and are fully configurable by the user.

ISO 16845 (Compliance to the ISO 11898)

• CAN ISO16845 Test Bench - fact sheet

Processor Interfaces

• MPC55xx External Bus Interface BFM - fact sheet
  
• PowerQUICCII Local Bus BFM - fact sheet

ARINC 429

• ARINC A429 Transmitter BFM - fact sheet
• ARINC A429 Receiver BFM - fact sheet

Serial Peripheral Interface Bus (SPI)

• SPI Master BFM - fact sheet
• SPI Slave BFM - fact sheet
  

VITAL2000 Standard Components (FREE)

• 74xxx245, 74xxx16245, 74xxx574 and many more.
  
• All models are VHDL-2008 compatible, architectures are VITAL_LEVEL1 for maximum performance.
• Development carried out with a DO-254 flow in mind: data sheet as requirement document, peer reviews, complete model verification.
• Rich documentation comes with each model:  user's manual, test bench, compilation and simulation Tcl scripts, files configuration index: the model can be integrated effortlessy in your DO-254 verification flow.
  

Under development

• UART
• Tricore's EBU

Interested? Wish a detailed data sheet? Please contact us:

Tel: +41 (0)789 564 207

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