SPI Master IP Core (DO-254)

                             VHDL Example                

As the name implies, the Serial Peripheral Interface (SPI) is primarily used to allow a microcontroller unit
(MCU) to communicate with peripheral devices.

The SPI Master IP Core is flexible enough to interface directly with numerous standard product peripherals (slaves) from several manufacturers.

Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices.

The SPI Master Core has been developed to DAL A according to the DO-254. For lower DAL levels reduced documentation sets are available. The cores are also available as a netlist for DAL D or projects not needing the full RTL source.

Develeast provides two separate IP Cores, one for the SPI Master Core and one for the SPI Slave Core. If the system needs to be configurable as master or slave both cores can easily be combined (VHDL code provided here).

SPI Master IP Core Block Diagram

KEY FEATURES:

• Fully compliant to the SPI Standard (Motorola’s M68H11 Reference Manual).
• Developed to DAL A (Design Assurance Level) according to RTCA DO-254/ED-80 (April, 2000)
• Configurable data rate (up to 1/1 with the clock input).
• Configurable:
  • phase (0 or 1)
  • polarity (0 or 1)
    
  • word size (any number of bits)
    
• Configurable number of slaves (any number).
• Simple interface to user’s logic.
• TMR (Triple Modular Redundancy) coded for SEU immunity (optional).
• Technology independent, can be synthesized to any FPGA/CPLD vendor.

IMPLEMENTATION DETAILS:

The following tables show some examples of implementing the SPI Master Core in different technologies and devices. Note that the SPI Master Core is technology independent, and therefore it can be implemented in any technology/device as long as it contains enough resources (Flip-Flops, gates, pins, etc.).

Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.

No constraints were added, so the results listed under the column "Maximum 'clk' Frequency" are the worst case scenario (no multicycle, false paths, etc. defined).

The following results are for an SPI Master Core with:

• g_SPI_WORD_LENGTH: 8
• g_NUM_OF_SLAVES:     1
• g_SCK_DIVIDER:         15
• without TMR

ACTEL

ALTERA

XILINX

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