ARINC 429 Transmitter IP Core (DO-254)
 
The A429 Tx Core implements a transmitter as specified in the ARINC Specification 429 Part 1-17.
This “Mark 33 Digital Information Transfer System (DITS)” specification defines how to transfer digital data between avionics systems elements. The transmission is done over a twisted and shielded pair of wires and bi-directional data flow is not permitted. An extra twisted and shielded pair of wires is used when data is required to flow both ways.
The A429 Tx Core has been developed to DAL A according to the DO-254. For lower DAL levels reduced documentation sets are available. The core is also available as a netlist for DAL D or projects not needing the full RTL source.
Develeast provides two separate IP Cores, one for the A429 Rx Coreand one for the A429 Tx Core
ARINC 429 Tx IP Core Block Diagram
KEY FEATURES:
- Compliant to ARINC Specification 429-17 (May 17, 2004)
- Design Assurance Level A according to RTCA DO-254/ED-80 (April, 2000)
- Single clock domain fully synchronous design
- Configurable data rate (selected by the Pulse Generator frequency)
- Interfaces to standard line drivers
- Simple interface to user's logic
- TMR (Triple Modular Redundancy) coded for SEU immunity (optional).
- Technology independent, can be synthesized to any FPGA/CPLD vendor.
IMPLEMENTATION DETAILS:
The following tables show some examples of implementing the A429 Tx Core in different technologies and devices. Note that the A429 Tx Core is technology independent, and therefore it can be implemented in any technology/device as long as it contains enough resources (Flip-Flops, gates, pins, etc.).
Unless otherwise specified all the runs have been performed with the default options of the respective tool. Register placement on the IO has been disabled.
No constraints were added, so the results listed under the column "Maximum 'clk' Frequency" are the worst case scenario (no multicycle, false paths, etc. defined).
ACTEL
|
FPGA Type
|
Maximum 'clk' Frequency
|
Logic Modules (CORE)
|
|
ProASIC3
(A3P015 68QFN I Std)
|
147 MHz
|
133
|
|
IGLOO
(AGL030V5 100VQFP I Std)
|
138 MHz
|
136
|
|
Fusion
(AFS090 180QFN I Std)
|
143 MHz
|
133
|
|
Axcelerator
(RTAX250S 208CQFP Mil Std)
|
199 MHz
|
SEQUENTIAL (R-cells): 43
COMB (C-cells): 79
|
ALTERA
|
FPGA Type
|
Maximum 'clk' Frequency
|
Flip-Flops
|
ALUTs
|
ALMs
|
Logic Cells
|
|
MAX II
(EPM240F100I5)
|
142 MHz
|
43
|
-
|
-
|
69
|
|
Cyclone III
(EP3C5E144I7)
|
> 350 MHz
|
43
|
-
|
-
|
71
|
|
Stratix II
(EP2S60F484I4)
|
> 400 MHz
|
43
|
29
|
34
|
-
|
|
Stratix III
(EP3SE110F780I3)
|
> 525 MHz
|
43
|
28
|
34
|
-
|
|
Stratix IV
(EP4SGX70HF35C2)
|
> 650 MHz
|
43
|
26
|
32
|
-
|
XILINX
|
FPGA Type
|
Maximum 'clk' Frequency
|
Flip-Flops
|
4-LUTs
|
Slices
|
Macrocells
|
|
CoolRunnerII
(XC2C128-6-TQ144)
|
126 MHz
|
43
|
-
|
-
|
58
|
|
Spartan3
(XC3S50-4PQ208)
|
197 MHz
|
43
|
112
|
61
|
-
|
|
Virtex2
(XC2V40-4FG256)
|
230 MHz
|
43
|
113
|
62
|
-
|
|
Virtex4
(XC4VLX15-12SF363)
|
> 430 MHz
|
44
|
116
|
62
|
-
|
|
Virtex5
(XC5VLX30-3FF324)
|
> 520 MHz
|
43
|
-
|
24
|
-
|
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